The present invention generally relates to semiconductor devices and more particularly to a semiconductor device formed on a (111) surface of a Si crystal and fabrication process thereof.
A gate insulation film of a MIS (metal/semiconductor/Si) transistor is subjected to various stringent requirements with regard to electric properties, including low leakage current, small surface state density, large hotcarrier resistance, and the like. Further, such a gate insulation film is required to provide high reliability. In order to meet for these stringent demands, it has been practiced conventionally to form the gate insulation film by a thermal oxidation of a Si substrate surface at a temperature of 800° C. or more.
However, a satisfactory oxide film that satisfies the requirements with regard to interface characteristics of the oxide/Si substrate interface, breakdown characteristics, and leakage current characteristics, is obtained only when the surface of the Si substrate has a (100) orientation as far as thermal oxidation process is used. When a thermal oxidation process is applied to a Si substrate having a surface orientation other than the (100) surface for forming a gate oxide film, there arises various problems in the gate oxide film such as increased surface state density at the oxide/Si substrate interface as compared with case of forming the Si oxide film on the (100)-oriented Si substrate. Further, the oxide film thus formed suffers from the problem of poor breakdown voltage characteristics or poor leakage current characteristics.
With regard to mobility, a MIS transistor shows a large mobility when formed on the (100)-oriented Si substrate. On the other hand, it is not possible to form a MIS transistor having a large driving power on a Si substrate having a different surface orientation.
Meanwhile, there is a need of introducing a metal material into a semiconductor substrate in high-speed semiconductor devices operable with a clock rate of about 10 GHz, for realizing attenuation-free signal transmission and cross-talk suppression. However, the use of high temperature process that requires a temperature of 550° C. or more in the device fabrication process raises the problem of deterioration of device performance caused by reaction between the metal layer and the semiconductor layer. Further, the use of high-temperature annealing process tends to facilitate diffusion of impurity elements introduced into the active region of the semiconductor layer, and there arises a difficulty in controlling the impurity distribution profile accurately. Thus, it has been necessary to avoid the use of thermal oxidation process conducted at the temperature of 800° C. or more in the fabrication process of highly miniaturized high-speed semiconductor devices.
Meanwhile, it is desirable to form a semiconductor device on a (111) surface of a Si crystal, in which Si atoms are arranged with a large surface density, in order to improve the driving power of the semiconductor device. Further, there is a demand of using a very thin gate insulation film having a dielectric constant larger than that of a Si oxide film. However, there has been no known process that enables formation of a high-quality high-dielectric film having a small surface state density and excellent electric property on a (111) surface of a Si crystal at low temperature.
In recent high-density semiconductor integrated circuits, it is generally practiced to form a shallow trench isolation (STI) structure on a Si substrate. In a semiconductor integrated circuit having such an STI structure, there arises a problem in that the thickness of an Si oxide film formed by a thermal oxidation process is tend to be reduced at the corner part of the device isolation groove as compared with the flat surface of the Si substrate. Associated therewith, the quality of the Si oxide film is deteriorated in such a corner part. Thus, there has been a reliability problem in the conventional semiconductor integrated circuit devices that uses an STI structure, such as degradation of leakage current characteristic or degradation of breakdown characteristic, particularly at the corner part of the STI structure. It is believed that the foregoing problem is caused by the (111) surface that appears at such a corner part of the device isolation groove when the device isolation groove is formed in an ordinary Si substrate having the (100) surface.
In order to avoid the foregoing problem, it has been practiced conventionally to form the STI structure such that the device isolation groove constituting the STI structure has a sidewall inclined with respect to the surface of the Si substrate with an angle of about 70 degrees or less. In other words, it has been practiced to provide a taper angle to the device isolation groove of the STI structure for minimizing the thinning of the Si oxide film at the corner part of the device isolation groove. In spite of such a measure, however, it has not been successful to suppress the degree of decrease of the film thickness below about 30%, and thus, the problem of increased leakage current or degradation of breakdown characteristic of the oxide film in the thinned part thereof has not been overcome. Further, the device having such a tapered device isolation groove has a drawback of increased width of the device isolation groove, and associated problem of reduced effective area on which semiconductor devices such as a transistor are formed. Thereby, increase of integration density of the semiconductor integrated circuit device has been impeded.
A polysilicon film formed on an insulation film shows a tendency that the Si crystals therein are oriented generally in the <111> direction. As long as conventional thermal oxidation process is used, it has been difficult to form a high-quality silicon gate oxide film on such a polysilicon film having the preferred orientation in the <111> direction. Thus, it has been difficult to form a high-speed semiconductor device of short gate length on a Si substrate formed on an insulation film such as a polysilicon film, and thus, it has been difficult to realize a three-dimensional integrated circuit by stacking a number of insulation films each carrying a semiconductor device.